Comprehensive Overview of Wafer-Level Packaging (WLP): Technology, Integration, Development, and Key Players

Wafer-Level Packaging (WLP) Overview

Wafer-Level Packaging (WLP) represents a specialized integrated circuit (IC) packaging technology characterized by the execution of all critical packaging processes while the silicon wafer remains intact—prior to dicing into individual chips. In its early designs, WLP explicitly required all input/output (I/O) connections to be entirely confined within the physical boundaries of a single die (fan-in configuration), achieving a true chip-scale package (CSP) structure. This sequential processing of the full wafer forms the foundation of fan-in WLP.

From a system integration perspective, the primary constraints of this architecture lie in:

1. Accommodating the required number of I/O connections within the limited space beneath the die.
2. Ensuring compatibility with subsequent printed circuit board (PCB) routing designs.

Driven by the relentless demand for miniaturization, higher operating frequencies, and cost reduction, WLP has emerged as a viable alternative when traditional packaging solutions (e.g., wire bonding or flip-chip interconnects) fail to meet these stringent requirements.

Evolution to Fan-Out WLP
 

The WLP landscape has expanded to include innovative packaging solutions that defy the limitations of standard fan-in structures—now classified as fan-out WLP (FO-WLP). The core process involves:

1. Die Embedding: Singulated dies are placed into a polymer or other substrate material with a standard wafer form factor, creating a reconstituted wafer.
2. RDL Expansion: The artificial wafer undergoes identical packaging processes as conventional wafers. Spacing between dies is engineered to preserve peripheral substrate areas, enabling fan-out redistribution layers (RDLs) that extend electrical interconnections beyond the original die footprint.

This breakthrough allows miniaturized dies to maintain compatibility with standard WLP ball-grid-array (BGA) pitches without physical enlargement. Consequently, WLP applicability now extends beyond monolithic silicon wafers to include hybrid wafer-level substrates, collectively categorized under WLP.

With the introduction of through-silicon vias (TSVs), integrated passive devices (IPDs), chip-first/chip-last fan-out techniques, MEMS/sensor packaging, and heterogeneous processor-memory integration, diverse WLP architectures have achieved commercialization. As illustrated in Figure 1, the spectrum spans:

• Low-I/O wafer-level chip-scale packages (WLCSPs)
• High-I/O-density, high-complexity fan-out solutions

These advancements have unlocked new dimensions in wafer-level packaging.

Figure 1 Heterogeneous integration using WLP

I. Wafer-Level Chip-Scale Packaging (WLCSP)
 

WLCSP emerged around 2000, primarily limited to single-die packaging. Due to its inherent design, WLCSP offers restricted multi-component integration capabilities. Figure 2 depicts a basic single-die WLCSP structure.

Figure 2 Basic Single Mode

Historical Context

Prior to WLCSP, most packaging processes (e.g., grinding, dicing, wire bonding) were mechanical and performed post-dicing (Figure 3).

Figure 3 Traditional Packaging Process Flow

WLCSP evolved naturally from wafer bumping—a practice IBM pioneered since the 1960s. The key distinction lies in using larger-pitch solder balls compared to traditional bumping. Unlike conventional packaging, nearly all WLCSP processes are executed in parallel on the full wafer (Figure 4).

Figure 4 Wafer-level Chip Scale Package (WLCSP) Process Flow

Advancements and Challenges

1. Miniaturization: WLCSP’s direct-die-as-package approach yields the smallest commercially viable form factor, widely adopted in compact mobile devices.
2. RDL Integration: Early versions relied solely on under-bump metallization (UBM) and solder balls. Rising complexity necessitated redistribution layers (RDLs) to decouple ball placement from bond pads, increasing structural intricacy.
3. Heterogeneous Integration: Innovations enabled "opossum-style" stacking—a thinned secondary die flip-chip bonded beneath the primary die, precisely fitted within solder ball gaps (Figure 5).

Figure 5 WLCSP, the second mold is installed on the lower side

3D Integration via TSVs

The advent of through-silicon vias (TSVs) facilitated double-sided connections in WLCSPs. While TSV integration employs "via-first" and "via-last" approaches, WLCSP adopts a "via-last" methodology. This allows:

• Top-side mounting of secondary dies (e.g., logic/analog dies on MEMS, or vice versa) (Figure 6).

Figure 6 WLCSP Through-Silicon Vias Dual-Side Mounting

• Replacement of chip-on-board (COB) packaging in automotive CMOS image sensors (e.g., 5.82mm × 5.22mm, 850μm-thick BSI packages with 3:1 aspect-ratio TSVs, 99.27% silicon content) (Figure 7).

Figure 7 (a) Three-dimensional view of the CIS-WLCSP structure; (b) Cross-section of CIS-WLCSP.

Reliability and Industry Dynamics

As process nodes shrink and WLCSP dimensions grow, reliability and chip-package interaction (CPI) challenges intensify—spanning manufacturing, handling, and PCB assembly.

• Six-Sided (6S) Protection: Solutions like fan-in M-Series (licensed from Deca Technologies) address sidewall protection needs.

• Supply Chain: Dominated by OSATs (ASE/SPIL, Amkor, JCET), with foundries (TSMC, Samsung) and IDMs (TI, NXP, STMicroelectronics) playing pivotal roles.

As a specialized provider of wafer-level packaging solutions, ZMSH offers advanced WLP technologies including fan-in and fan-out configurations to meet the growing demands of semiconductor applications. We provide end-to-end services from design to volume production, with expertise in high-density interconnects and heterogeneous integration for MEMS, sensors and IoT devices. Our solutions address key industry challenges in miniaturization and performance optimization, helping clients accelerate product development cycles. With extensive experience in bumping, RDL formation and final testing, we deliver reliable, cost-effective packaging solutions tailored to specific application requirements.