Gallium nitride power devices have developed primarily around lateral HEMT architectures. These devices have become increasingly important in fast chargers, server power supplies, motor drives and other high-frequency power-conversion applications.

In 2026, however, interest in vertical GaN is increasing.

The key difference is the direction of current flow.

In a conventional lateral GaN HEMT, current travels mainly along the surface of the epitaxial structure. In a vertical device, current travels through the thickness of the semiconductor.

This change may allow GaN to move toward higher voltage and higher current levels without continuously increasing the lateral chip area.

The challenge is the substrate.

Why Vertical GaN Has Traditionally Needed Native GaN

Vertical power devices require current to pass through the epitaxial structure toward the backside contact.

Bulk GaN substrates are well suited to this architecture because the substrate and epitaxial layer share essentially the same crystal system.

This can provide:

• lower threading-dislocation density;

• improved epitaxial compatibility;

• a direct vertical conduction path;

• reduced lattice-mismatch stress;

• better support for thick high-voltage drift layers.

However, native GaN substrates remain considerably smaller and more expensive than mainstream silicon wafers.

This limits the economic advantage of vertical GaN for mass-market power electronics.

If vertical GaN could instead be fabricated on large silicon wafers, the economics could change substantially.

The Problem With Conventional GaN-on-Si Buffers

Growing GaN directly on silicon is difficult.

GaN and silicon have different lattice constants and thermal-expansion coefficients.

As a result, conventional GaN-on-Si structures normally require engineered buffer layers to control:

• stress;

• cracking;

• dislocations;

• wafer bow;

• electrical isolation.

These buffer layers work well for lateral devices.

For vertical devices, however, a highly resistive buffer can become a major problem because the current needs to pass through the structure.

The same layer that helps isolate a lateral GaN transistor can block vertical current flow.

This is why low-resistance buffer engineering is becoming an important research direction.

A New Low-Resistance Interlayer Approach

In 2026, researchers from Japan reported a new approach for growing GaN on Si(111) using an extremely thin amorphous-like interlayer.

The method forms an approximately sub-nanometer-scale interlayer between silicon and GaN that helps accommodate the lattice mismatch while maintaining low vertical electrical resistance.

The researchers demonstrated that the approach could support subsequent MOCVD GaN growth while maintaining robust thermal stability and vertical current conduction.

The significance is not simply another GaN buffer-layer structure.

It addresses one of the central contradictions in vertical GaN-on-Si:

the interface must absorb crystal mismatch without becoming an electrical barrier.

If such structures can be scaled reliably, they could make silicon a more practical platform for vertical GaN devices.

200 mm Silicon Makes the Concept More Interesting

Silicon offers one major advantage that native GaN does not yet provide economically:

large-diameter semiconductor infrastructure.

200 mm silicon fabs already contain mature equipment for:

• lithography;

• implantation;

• metallization;

• inspection;

• wafer handling;

• automated process control.

Research published in 2026 demonstrated avalanche behavior in pseudo-vertical GaN p-n diodes fabricated using GaN epitaxy on 200 mm silicon substrates. The devices reached approximately 805 V without dedicated edge termination, illustrating how GaN-on-Si research is beginning to move beyond traditional lateral transistor structures.

This does not mean vertical GaN-on-Si is ready to replace existing GaN or SiC platforms.

But it demonstrates why researchers continue to investigate ways of combining vertical GaN device physics with large silicon wafer economics.

Vertical GaN Is Also Moving Into System-Level Testing

Another important change in 2026 is that vertical GaN is moving beyond individual test devices.

Researchers demonstrated a 10.4 kW three-phase inverter using vertical GaN trench MOSFETs.

The work also identified reliability issues related to threshold-voltage shift and increased on-resistance, highlighting the importance of improving the MOS interface and p-body design.

This is an important stage of technology development.

Laboratory breakdown voltage alone does not prove that a power semiconductor is ready for practical systems.

Real inverters expose devices to:

• switching stress;

• temperature cycles;

• high current;

• gate stress;

• transient voltage;

• parallel-device imbalance.

System-level demonstrations reveal reliability problems that may not appear in simple wafer-level measurements.

Why the GaN Wafer Still Matters

Whether vertical GaN is fabricated on native GaN or silicon, wafer quality remains fundamental.

Important parameters include:

• threading dislocation density;

• wafer bow and warp;

• epitaxial thickness uniformity;

• drift-layer doping uniformity;

• surface roughness;

• crack density;

• backside contact compatibility.

For high-voltage vertical devices, thick GaN drift layers become particularly important.

Small variations in thickness or doping can translate into variations in breakdown voltage and on-resistance across the wafer.

This means vertical GaN manufacturing requires not only a good transistor structure but also extremely consistent epitaxial material.

Native GaN Will Still Have an Advantage

GaN-on-silicon research should not be interpreted as evidence that native GaN substrates are becoming unnecessary.

Native GaN remains attractive for the highest-performance vertical devices because it can provide very low defect density and excellent crystal compatibility.

2026 reviews of vertical GaN technology continue to identify native GaN as an important platform for high-voltage operation, while also emphasizing substrate cost as a major obstacle to broad commercialization.

The market may therefore develop along two paths.

Native GaN could serve demanding applications where material quality justifies the higher substrate cost.

GaN-on-Si could target high-volume applications where manufacturing scale and cost are more important.

The Next Question Is Manufacturing Yield

Vertical GaN has already demonstrated impressive laboratory performance.

The next challenge is not simply achieving another breakdown-voltage record.

The industry needs to determine whether vertical devices can be manufactured with:

• stable wafer-to-wafer epitaxy;

• acceptable defect density;

• reproducible MOS interfaces;

• high device yield;

• long-term reliability;

• competitive cost.

If low-resistance GaN-on-Si buffer technology continues to improve, silicon may eventually provide a bridge between advanced GaN device physics and high-volume wafer manufacturing.

That makes vertical GaN-on-Si one of the most interesting GaN wafer developments to watch beyond 2026.