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Al₂O₃ Sapphire Wafer, Off C-Axis Toward M-Plane 8°, Diameters: 2"– 8", Custom Thickness

12inch Diameter 300mm SIC Substrate Epitaxial Polished Wafer Silicon Carbide Ingot Prime Grade 4H-N Type Conductive Solar Photovoltaic

Sapphire Custom-Shaped Sapphire View Windows Optical Glass high hardness

Polished Sapphire Tube Single Crystal Al₂O₃ Optical Component

Customizable 40mm/42mm Round Sapphire Watch Case In Magenta

6'' 8'' Ultra Thick SiO2 Single Crystal 10um 20um 25um Dry Wet Oxide Layer 0.1μM 25μM

Si3Nx Coating Wafer With Resistivity 1 - 10ohm No Defects

3C-SiC Substrate N type Product Grade For 5G Communications

2 Inch Quartz Glass Wafer DSP SSP Diameter 50.8mm

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Square Rectangle Sapphire Optical Windows , Single Crystal Glass For LED Chip

Al2O3 Single Crystal Sapphire Glass Lens Applied Semiconductor Substrates

Surface Polished Synthetic Sapphire Rod , Sapphire Ingot High Dielectric Constant

2inch 3inch Dia100m 4H-N Type Silicon Carbide Wafer Production Grade For Semiconductor Device

Dummy Grade 6Inch Sic Substrate Wafer Dia150mm 4H-N 500mm Thickness

Raw Al2O3 Sapphire Parts , Sapphire Single Crystal Glass Block High Thermal Conductivity

Al2O3 Single Crystal Sapphire Optical Windows Custom Shape With Square Round Hole

Al2O3 Crystal Materials Step Sapphire Optical Windows With High Thermal Conductivity

High Purity Sapphire Wafer , Sapphire Crystal Glass Optical Steps Polished Lens

Optical Glass Plate , Single Crystal Glass For Wrist Watch Glass Lens

4H-SEMI Polished Sic Wafer lens 2INCH 3INCH 4INCH 9.0 Hardness For Device Material

Y- 42°LiTaO3 LiNbO3 Wafers 4 Inch Dia 100 Mm With Thickness 46mm

Undoped Semi - Insulating Gallium Nitride Wafer HVPE And Template Type

Dia 50.8mm 2 Inch Gallium Arsenide Wafer For Semiconductor Substrate

Black Indium Phosphide Wafer , Semiconductor Wafer For LD Application

Al2O3 Crystal Sapphire Cover Glass Double Side Polished Customized Shape

Wearable Synthetic Ruby Custom Shape Red Titanium Sapphire Laser Crystals

4 Inch IC Silicon Wafer Optical Lens Prime Grade For Optoelectronics

Black 8 Inch IC Silicon Wafer Silicon Ingots Polysilicon For Semiconductor Process

Rectangle Shape Silica Fused Quartz Plate Double Side Polished DSP GS1 GS2 GS3 Grade

COMPANY INTRODUCTION

SHANGHAI FAMOUS TRADE CO.,LTD

SHANGHAI FAMOUS TRADE CO.,LTD. locates in the city of Shanghai, Which is the best city of China, and our factory is founded in Wuxi city in 2014.We specialize in processing a varity of materials into wafers, substrates and custiomized optical glass parts.components widely used in electronics, optics, optoelectronics and many other fields. We also have been working closely with many domestic and oversea universities, research institutions and companies, provide customized products and services ...

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Company News

2025/08/20

Key Raw Materials in Semiconductor Manufacturing: Types of Wafer Substrates

Key Raw Materials in Semiconductor Manufacturing: Types of Wafer Substrates Wafer substrates serve as the physical carriers of semiconductor devices, with their material properties directly influencing device performance, cost, and application scope. Below are the primary types of wafer substrates and their respective advantages and disadvantages: 1. Silicon (Si) Market Share: Dominates over 95% of the global semiconductor market. Advantages: Low Cost: Abundant raw materials (silicon dioxide) and mature manufacturing processes enable significant economies of scale. High Process Compatibility: Highly mature CMOS technology supports nanoscale fabrication (e.g., 3nm nodes). Excellent Crystal Quality: Capable of producing large-sized (12-inch primary, 18-inch under development) low-defect single crystals. Stable Mechanical Properties: Easy to cut, polish, and process. Disadvantages: Narrow Bandgap (1.12 eV): High leakage current at elevated temperatures, limiting efficiency in power devices. Indirect Bandgap: Extremely low light emission efficiency, unsuitable for optoelectronic devices (e.g., LEDs, lasers). Limited Electron Mobility: Inferior high-frequency performance compared to compound semiconductors. ZMSH's silicon wafers 2. Gallium Arsenide (GaAs) Applications: High-frequency RF devices (5G/6G), optoelectronic devices (lasers, solar cells). Advantages: High Electron Mobility (5–6× that of silicon): Ideal for high-speed, high-frequency applications (mmWave communications). Direct Bandgap (1.42 eV): Efficient photoelectric conversion, forming the foundation of infrared lasers and LEDs. Thermal/Radiation Resistance: Suitable for aerospace and high-temperature environments. Disadvantages: High Cost: Scarce material with complex crystal growth (prone to dislocations); wafer sizes are small (6-inch primary). Mechanical Brittleness: Prone to fragmentation, resulting in low processing yields. Toxicity: Strict control required for arsenic handling. ZMSH's GaAs wafers 3. Silicon Carbide (SiC) Applications: High-temperature/high-voltage power devices (EV inverters, charging piles), aerospace. Advantages: Wide Bandgap (3.26 eV): Withstands high voltages (breakdown field strength 10× that of silicon) and operates at >200°C. High Thermal Conductivity (3× that of silicon): Efficient heat dissipation enhances system power density. Low Switching Losses: Improves power conversion efficiency. Disadvantages: Challenging Substrate Preparation: Slow crystal growth (>1 week) and difficult defect control (microtubes, dislocations); costs 5–10× that of silicon. Small Wafer Sizes: Mainstream 4–6 inches; 8-inch development ongoing. Difficult Processing: High hardness (Mohs 9.5) makes cutting and polishing time-consuming. ZMSH's SiC wafers 4. Gallium Nitride (GaN) Applications: High-frequency power devices (fast chargers, 5G base stations), blue LEDs/lasers. Advantages: Ultra-High Electron Mobility + Wide Bandgap (3.4 eV): Combines high-frequency (>100 GHz) and high-voltage characteristics. Low On-Resistance: Reduces device power consumption. Heterogeneous Epitaxy Compatibility: Often grown on silicon, sapphire, or SiC substrates to lower costs. Disadvantages: Difficulty in Bulk Crystal Growth: Mainstream relies on heterogeneous epitaxy, with lattice mismatch-induced defects. High Cost: Self-supporting GaN substrates are expensive (2-inch wafers can cost thousands of dollars). Reliability Challenges: Current collapse effect requires optimization. ZMSH's GaN wafers 5. Phosphorus-Indium (InP) Applications: High-speed optoelectronics (lasers, detectors), terahertz devices. Advantages: Ultra-High Electron Mobility: Supports >100 GHz high-frequency operation (superior to GaAs). Direct Bandgap with Wavelength Matching: Critical for 1.3–1.55μm fiber-optic communications. Disadvantages: Brittleness and High Cost: Substrate prices are over 100× that of silicon; wafer sizes are small (4–6 inches). ZMSH's InP wafers 6. Sapphire (Al₂O₃) Applications: LED lighting (GaN epitaxial substrates), consumer electronics covers. Advantages: Low Cost: Cheaper than SiC/GaN substrates. Chemical Stability: Corrosion-resistant and insulating. Transparency: Suitable for vertical-structure LEDs. Disadvantages: Lattice Mismatch with GaN (>13%): Requires buffer layers to reduce epitaxial defects. Poor Thermal Conductivity (≈1/20 that of silicon): Limits performance in high-power LEDs. ZMSH's sapphire wafers 7. Aluminum Oxide/Ceramic Substrates (e.g., AlN, BeO) Applications: Heat dissipation substrates for high-power modules. Advantages: Insulation + High Thermal Conductivity (AlN: 170–230 W/m·K): Ideal for high-density packaging. Disadvantages: Non-Single-Crystal: Cannot directly grow devices; used solely as packaging substrates. ZMSH's Alumina ceramic substrate 8. Specialized Substrates SOI (Silicon on Insulator): Structure: Silicon/silicon dioxide/silicon sandwich. Advantages: Reduces parasitic capacitance, radiation hardness, and leakage current (used in RF, MEMS). Disadvantages: 30–50% higher cost than bulk silicon. Quartz (SiO₂): Used in photomasks, MEMS; heat-resistant but brittle. Diamond: Highest thermal conductivity (>2000 W/m·K) under development for extreme heat dissipation. ZMSH's SOI wafer,Quartz wafer,Diamond substrate Summary Comparison Table Substrate Bandgap Energy (eV) Electron Mobility (cm²/Vs) Thermal Conductivity (W/mK) Mainstream Size Core Applications Cost Si 1.12 1,500 150 12-inch Logic/Storage Chips Lowest GaAs 1.42 8,500 55 4-6-inch RF/Opto-electronic Devices High SiC 3.26 900 490 6-inch (R&D 8-inch) Power Devices/Electric Vehicles Extremely High GaN 3.4 2,000 130-170 4-6-inch (Heteroepitaxy) Fast Charging/RF/LED High (Heteroepitaxy, etc.) InP 1.35 5,400 70 4-6-inch Optical Communications/Terahertz Extremely High Sapphire 9.9 (Insulator) - 40 4-8-inch LED Substrate Low Key Factors for Selection Performance Requirements: High-frequency applications favor GaAs/InP; high-voltage/high-temperature applications require SiC; optoelectronics prefer GaAs/InP/GaN. Cost Constraints: Consumer electronics prioritize silicon; high-end fields accept premium pricing for SiC/GaN. Integration Complexity: Silicon CMOS compatibility remains unrivaled. Thermal Management: High-power devices prioritize SiC or diamond-based GaN. Supply Chain Maturity: Silicon > Sapphire > GaAs > SiC > GaN > InP. Future Trends Heterogeneous integration (e.g., GaN on silicon, SiC on GaN) will balance performance and cost, driving advancements in 5G, electric vehicles, and quantum computing. ZMSH's Services As an integrated manufacturing and trading semiconductor materials comprehensive service provider, we deliver full-chain product supply chain solutions—from wafer substrates (Si/GaAs/SiC/GaN, etc.) to photoresists and CMP polishing materials. Leveraging self-developed production bases and a globalized supply chain network, we combine rapid response capabilities with professional technical support to empower clients in achieving stable supply chain operations and technological innovation win-win outcomes.

2025/08/13

Large-Format Laser Dicing Equipment: Core Technology for Future 8-Inch SiC Wafer Production

Large-Format Laser Dicing Equipment: Core Technology for Future 8-Inch SiC Wafer Production Silicon Carbide (SiC) represents not only a critical technology for national defense security but also a key focus for the global automotive and energy industries. As the initial processing step for SiC monocrystalline materials, wafer dicing quality fundamentally determines subsequent thinning and polishing performance. Conventional slicing processes tend to generate surface/subsurface cracks, increasing breakage rates and manufacturing costs. Therefore, controlling surface crack damage is crucial for advancing SiC device manufacturing technology. ZMSH's wafer thinning equipment Current SiC ingot dicing faces two major challenges: High material loss rate in traditional multi-wire sawing. Due to SiC's extreme hardness and brittleness, cutting/grinding/polishing processes encounter severe warping and cracking issues. Infineon data shows traditional diamond wire sawing achieves only 50% material utilization during slicing, with total losses reaching 75% (∼250μm per wafer) after polishing. Prolonged processing cycles and low throughput. International production statistics indicate 10,000 wafers require ∼273 days of continuous operation. Meeting market demand necessitates massive wire saw deployments while suffering from high surface roughness and severe pollution (slurry waste, wastewater). To address these challenges, Prof. Xiangqian Xiu's team at Nanjing University has developed large-format laser dicing equipment that significantly reduces material loss and improves productivity. For a 20mm SiC ingot, laser technology doubles the yield compared to wire sawing. Additionally, laser-cut wafers exhibit superior geometric characteristics, enabling 200μm thickness for further yield increase. This project's competitive advantages include: Completed prototype development for 4-6" semi-insulating SiC wafer dicing/thinning Achieved 6" conductive SiC ingot slicing Ongoing 8" ingot dicing verification Features 50% shorter processing time, higher annual throughput, and

2025/08/12

Comprehensive Overview of Wafer-Level Packaging (WLP): Technology, Integration, Development, and Key Players

Comprehensive Overview of Wafer-Level Packaging (WLP): Technology, Integration, Development, and Key Players Wafer-Level Packaging (WLP) Overview Wafer-Level Packaging (WLP) represents a specialized integrated circuit (IC) packaging technology characterized by the execution of all critical packaging processes while the silicon wafer remains intact—prior to dicing into individual chips. In its early designs, WLP explicitly required all input/output (I/O) connections to be entirely confined within the physical boundaries of a single die (fan-in configuration), achieving a true chip-scale package (CSP) structure. This sequential processing of the full wafer forms the foundation of fan-in WLP. From a system integration perspective, the primary constraints of this architecture lie in: Accommodating the required number of I/O connections within the limited space beneath the die. Ensuring compatibility with subsequent printed circuit board (PCB) routing designs. Driven by the relentless demand for miniaturization, higher operating frequencies, and cost reduction, WLP has emerged as a viable alternative when traditional packaging solutions (e.g., wire bonding or flip-chip interconnects) fail to meet these stringent requirements. Evolution to Fan-Out WLP The WLP landscape has expanded to include innovative packaging solutions that defy the limitations of standard fan-in structures—now classified as fan-out WLP (FO-WLP). The core process involves: Die Embedding: Singulated dies are placed into a polymer or other substrate material with a standard wafer form factor, creating a reconstituted wafer. RDL Expansion: The artificial wafer undergoes identical packaging processes as conventional wafers. Spacing between dies is engineered to preserve peripheral substrate areas, enabling fan-out redistribution layers (RDLs) that extend electrical interconnections beyond the original die footprint. This breakthrough allows miniaturized dies to maintain compatibility with standard WLP ball-grid-array (BGA) pitches without physical enlargement. Consequently, WLP applicability now extends beyond monolithic silicon wafers to include hybrid wafer-level substrates, collectively categorized under WLP. With the introduction of through-silicon vias (TSVs), integrated passive devices (IPDs), chip-first/chip-last fan-out techniques, MEMS/sensor packaging, and heterogeneous processor-memory integration, diverse WLP architectures have achieved commercialization. As illustrated in Figure 1, the spectrum spans: Low-I/O wafer-level chip-scale packages (WLCSPs) High-I/O-density, high-complexity fan-out solutions These advancements have unlocked new dimensions in wafer-level packaging. Figure 1 Heterogeneous integration using WLP I. Wafer-Level Chip-Scale Packaging (WLCSP) WLCSP emerged around 2000, primarily limited to single-die packaging. Due to its inherent design, WLCSP offers restricted multi-component integration capabilities. Figure 2 depicts a basic single-die WLCSP structure. Figure 2 Basic Single Mode Historical Context Prior to WLCSP, most packaging processes (e.g., grinding, dicing, wire bonding) were mechanical and performed post-dicing (Figure 3). Figure 3 Traditional Packaging Process Flow WLCSP evolved naturally from wafer bumping—a practice IBM pioneered since the 1960s. The key distinction lies in using larger-pitch solder balls compared to traditional bumping. Unlike conventional packaging, nearly all WLCSP processes are executed in parallel on the full wafer (Figure 4). Figure 4 Wafer-level Chip Scale Package (WLCSP) Process Flow Advancements and Challenges Miniaturization: WLCSP’s direct-die-as-package approach yields the smallest commercially viable form factor, widely adopted in compact mobile devices. RDL Integration: Early versions relied solely on under-bump metallization (UBM) and solder balls. Rising complexity necessitated redistribution layers (RDLs) to decouple ball placement from bond pads, increasing structural intricacy. Heterogeneous Integration: Innovations enabled "opossum-style" stacking—a thinned secondary die flip-chip bonded beneath the primary die, precisely fitted within solder ball gaps (Figure 5). Figure 5 WLCSP, the second mold is installed on the lower side 3D Integration via TSVs The advent of through-silicon vias (TSVs) facilitated double-sided connections in WLCSPs. While TSV integration employs "via-first" and "via-last" approaches, WLCSP adopts a "via-last" methodology. This allows: Top-side mounting of secondary dies (e.g., logic/analog dies on MEMS, or vice versa) (Figure 6). Figure 6 WLCSP Through-Silicon Vias Dual-Side Mounting Replacement of chip-on-board (COB) packaging in automotive CMOS image sensors (e.g., 5.82mm × 5.22mm, 850μm-thick BSI packages with 3:1 aspect-ratio TSVs, 99.27% silicon content) (Figure 7). Figure 7 (a) Three-dimensional view of the CIS-WLCSP structure; (b) Cross-section of CIS-WLCSP. Reliability and Industry Dynamics As process nodes shrink and WLCSP dimensions grow, reliability and chip-package interaction (CPI) challenges intensify—spanning manufacturing, handling, and PCB assembly. Six-Sided (6S) Protection: Solutions like fan-in M-Series (licensed from Deca Technologies) address sidewall protection needs. Supply Chain: Dominated by OSATs (ASE/SPIL, Amkor, JCET), with foundries (TSMC, Samsung) and IDMs (TI, NXP, STMicroelectronics) playing pivotal roles. As a specialized provider of wafer-level packaging solutions, ZMSH offers advanced WLP technologies including fan-in and fan-out configurations to meet the growing demands of semiconductor applications. We provide end-to-end services from design to volume production, with expertise in high-density interconnects and heterogeneous integration for MEMS, sensors and IoT devices. Our solutions address key industry challenges in miniaturization and performance optimization, helping clients accelerate product development cycles. With extensive experience in bumping, RDL formation and final testing, we deliver reliable, cost-effective packaging solutions tailored to specific application requirements.

Gallium Nitride Wafer

Sapphire Wafer

SiC Substrate

Sapphire Optical Windows

IC Silicon Wafer

Synthetic Sapphire Rod

Fused Quartz Plate

Sapphire Parts

Synthetic Gemstone

Semiconductor Equipment

LiNbO3 Wafer

GaAs Wafer

Indium Phosphide Wafer

Ceramic Substrate

Lab Wrapper

Al₂O₃ Sapphire Wafer, Off C-Axis Toward M-Plane 8°, Diameters: 2"– 8", Custom Thickness

12inch Diameter 300mm SIC Substrate Epitaxial Polished Wafer Silicon Carbide Ingot Prime Grade 4H-N Type Conductive Solar Photovoltaic

Sapphire Custom-Shaped Sapphire View Windows Optical Glass high hardness

Polished Sapphire Tube Single Crystal Al₂O₃ Optical Component

Customizable 40mm/42mm Round Sapphire Watch Case In Magenta

6'' 8'' Ultra Thick SiO2 Single Crystal 10um 20um 25um Dry Wet Oxide Layer 0.1μM 25μM

Si3Nx Coating Wafer With Resistivity 1 - 10ohm No Defects

3C-SiC Substrate N type Product Grade For 5G Communications

2 Inch Quartz Glass Wafer DSP SSP Diameter 50.8mm

SHANGHAI FAMOUS TRADE CO.,LTD

SiC Substrate

High Purity un-doped Silicon Carbide sic Wafer , 6Inch 4H-Semi Sic Silicon Carbide Substrate

2 Inch 6H - Semi Silicon Carbide Wafer Low Power Consumption For Detector

4inch Sic Ingot Silicon Carbide 5 - 15mm Thickness for semiconductors

Sapphire Wafer

Semiconductor Wafer Custom Sapphire Glass / Sapphire Windows Special Orientation

sapphire wafer Thickness 0.43mm Sapphire Components Customized Size And Orientations

Square Sapphire Wafer / Sapphire Crystal Glass 10x10mm 5x5mm For Optical Lens

Gallium Nitride Wafer

Laser Projection Display Gallium Nitride GaN Wafer 350um Thickness

2inch 4inch free-standing GaN Gallium Nitride Substrates Template for led

2INCH 4INCH NPSS/FSS AlN template on sapphire EPI-wafer AlN-On-Sapphire wafer